5G mmWave PAAM Development Platform
Avnet and Fujikura have created a highly integrated 5G FR2 phased array antenna development platform for mmWave frequency bands. Through real-time control of digital and RF settings using Avnet’s RFSoC Explorer® software, developers can create and prototype wireless applications with AMD Xilinx’s Zynq® UltraScale+™ RFSoC Gen3 and Fujikura’s FutureAcess™ Phased Array Antenna Module (PAAM). Seamless expansion to multiple PAAMs enables advanced beamforming scenarios and sub-array topologies.
The PAAM platform consists of the Fujikura PAAM evaluation board (2 versions: 26.50-29.50GHZ or 24.25-27.50GHZ), the AMD ZCU208 EVK, and the Avnet RFSoC Explorer MATLAB application.
Highlights
Target Applications:
- 5G FR2 bands 24-30 GHz
- 5G Private Networks
- Advanced beamforming scenarios and sub-array topologies with multiple PAAMs
Key Features:
- 64-element, dual-polarized phased array antenna module, calibration-free
- Independent gain/phase control by True-Time-Delay–Type phase shifters
- 4.9 GHz I/F between RFSoC and Fujikura PAAM with integrated LO frequency converter
- High power-efficiency optimization with >20% peak PAE
- Accurate beam steering for ±60° degrees with fine resolution
- Broad coverage without dead spot with >30,000 beams
- Zynq UltraScale+ RFSoC ZU48DR with integrated gigasample data converters and programmable gain control
- 8x 14-bit 5 GSPS ADCs, 8x 14-bit 9.85 GSPS DACs
- Control AMD RFSoC and Fujikura 5G PAAM in MATLAB
- Hardware/software co-design through SoC Blockset from MathWorks
Kit Includes:
- Fujikura Type-C PAAM Evaluation Board 26.50 - 29.50GHz with MicroZed controller
- AMD Zynq UltraScale+ RFSoC ZCU208 EVK
- Avnet RFSoC Explorer MATLAB Application
Specifications
| Family: | AAG |
| Release date: | 0000-00-00 00:00:00 |
| Chipset: | Zynq UltraScale+ RFSoC ZU48DR |
| Firmware: | Source code available for MicroZed controller on Fujikura FutureAccess PAAM, Vivado 2023.1 |
| Memory: | 4GB 64-bit DDR4 programmable logic memory / 4GB 64-bit DDR4 processor system memory |
| Chipset Brand: | AMD |
| Wireless Module: | AMD RFSoC RF Mezzanine Card 2.0 interface for RF expansion |
| Product Brief: | FY25_1482_Avnet-Fujikura_5G_mmWave_Product_Brief.pdf |
| Target_Applications_1: | 5G FR2 bands 24-30 GHz |
| Target_Applications_2: | 5G Private Networks |
| Target_Applications_3: | Advanced beamforming scenarios and sub-array topologies with multiple PAAMs |
| Kit_Includes_1: | Fujikura Type-C PAAM Evaluation Board 26.50 - 29.50GHz with MicroZed controller |
| Kit_Includes_2: | AMD Zynq UltraScale+ RFSoC ZCU208 EVK |
| Kit_Includes_3: | Avnet RFSoC Explorer MATLAB Application |
| Key_Features_1: | 64-element, dual-polarized phased array antenna module, calibration-free |
| Key_Features_2: | Independent gain/phase control by True-Time-Delay–Type phase shifters |
| Key_Features_3: | 4.9 GHz I/F between RFSoC and Fujikura PAAM with integrated LO frequency converter |
| Key_Features_4: | High power-efficiency optimization with >20% peak PAE |
| Key_Features_5: | Accurate beam steering for ±60° degrees with fine resolution |
| Key_Features_6: | Broad coverage without dead spot with >30,000 beams |
| Key_Features_7: | Zynq UltraScale+ RFSoC ZU48DR with integrated gigasample data converters and programmable gain control |
| Key_Features_8: | 8x 14-bit 5 GSPS ADCs, 8x 14-bit 9.85 GSPS DACs |
| Key_Features_9: | Control AMD RFSoC and Fujikura 5G PAAM in MATLAB |
| Key_Features_10: | Hardware/software co-design through SoC Blockset from MathWorks |
| Product_Brief_Name: | FY25_1482_Avnet-Fujikura_5G_mmWave_Product_Brief.pdf |
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